1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com hi-reliability product edi81256c 256kx1 high speed monolithic sram cmos features n 128kx8 bit cmos static n random access memory ? fast access times of 35, 45, 55ns ? data retention function (lp) ? ttl compatible inputs and outputs ? fully static, no clocks n jedec approved pinouts ? 24 pin ceramic dip (package 3) ? 28 pad ceramic lcc (package 14) ? 28 lead ceramic flatpack (package 79) n single +5v ( 10%) supply operation 28 flatpack top view july 1996 rev. 8 pin description d data input q data output a 0-17 address inputs we write enable cs chip select v cc power (+5v 10%) v ss ground nc not connected block diagram memory array address buffer address decoder i/o circuits a -17 q cs we d fig. 1 pin configuration the edi88128cs is a high speed, high performance, megabit density monolithic cmos static ram organized as 128kx8. the device has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. an automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. a low power version with 2v data retention (edi88128lps) is also available for battery back-up opperation. military product is available compliant of mil-prf-38535. 24 dip top view a12 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 v cc a17 a16 a15 a14 a13 a11 a10 a9 d cs a a1 a2 a3 a4 a5 a6 a7 a8 q we v ss 4 5 6 7 8 9 10 11 12 nc a3 a4 a5 a6 a7 a8 q nc 26 25 24 23 22 21 20 19 18 nc a16 a15 a14 a13 a12 a11 a10 nc 3 2 1 28 27 a2 a1 a vcc a17 13 14 15 16 17 we vss cs d a9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v cc a17 a16 a15 a14 a13 nc nc a12 a11 a10 a9 d cs a a1 a2 a3 a4 a5 nc nc a6 a7 a8 q we v ss 28 clcc top view
2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi81256c absolute maximum ratings parameter unit voltage on any pin relative to vss -0.5 to 7.0 v operating t emperature t a (ambient) commercial 0 to +70 c industrial -40 to +85 c military -55 to +125 c storage temperature, plastic -65 to +150 c power dissipation 1 w output current 20 ma junction temperature, t j 175 c recommended operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 000v input high voltage v ih 2.2 6.0 v input low voltage v il -0.3 +0.8 v parameter symbol condition max unit address lines c i v in = vcc or vss, f = 1.0mhz 10 pf data lines c d/q v out = vcc or vss, f = 1.0mhz 12 pf these parameters are sampled, not 100% tested. capacitance (t a = +25 c) truth table cs we mode output power h x standby high z icc 2 , icc 3 l h output deselect high z icc 1 l h read data out icc 1 l l write data in icc 1 note: stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol conditions units min typ max input leakage current i li v in = 0v to v cc -5 +5 m a output leakage current i lo v i/o = 0v to v cc -5 +5 m a operating power supply current i cc1 we, cs = v il , i i/o = 0ma, min cycle 80 120 ma standby (ttl) power supply current i cc2 cs 3 v ih , v in v il , v in 3 v ih 220ma cs 3 v cc -0.2v c13ma full standby power supply current i cc3 v in 3 vcc -0.2v or v in 0.2v lp 0.5 1.5 ma output low voltage v ol i ol = 8.0ma 0.4 v output high voltage v oh i oh = -4.0ma 2.4 v note: dc test conditions: v il = 0.3v, v ih = vcc -0.3v dc characteristics (v cc = 5v, t a = -55 c to +125 c) lcc, dip, flatpack
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi81256c input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load figure 1 note: for t ehqz , t ghqz and t wlqz , cl = 5pf figure 2) 30pf 480 w vcc q figure 1 figure 2 255 w 5pf 480 w vcc q 255 w ac test conditions ac characteristics C read cycle (v cc = 5.0v, v ss = 0v, t a = 0 c to +70 c) symbol 35ns 45ns 55ns parameter jedec alt. min max min max min max units read cycle time t avav t rc 35 45 55 ns address access time t avqv t aa 35 45 55 ns chip enable access time t elqv t acs 35 45 55 ns chip enable to output in low z (1) t elqx t clz 55 5ns chip disable to output in high z (1) t ehqz t chz 020 0 20 0 20ns output hold from address change t avqx t oh 55 5ns chip enable to power up (1) t elicch t pu 00 0ns chip enable to power down (1) t ehiccl t pd 35 45 55 ns 1. this parameter is guaranteed by design but not tested. ac characteristics C write cycle (v cc = 5.0v, v ss = 0v, t a = 0 c to +70 c) symbol 35ns 45ns 55ns parameter jedec alt. min max min max min max units write cycle time t avav t wc 35 45 55 ns chip enable to end of write t elwh t cw 30 35 45 ns t eleh t cw 30 35 45 ns address setup time t avwl t as 000 ns t avel t as 000 ns address valid to end of write t avwh t aw 30 35 45 ns t aveh t aw 30 35 45 ns write pulse width t wlwh t wp 25 25 30 ns t wleh t wp 25 25 30 ns write recovery time t whax t wr 555 ns t ehax t wr 555 ns data hold time t whdx t dh 000 ns t ehdx t dh 000 ns write to output in high z (1) t wlqz t whz 015 0 150 20 ns data to write time t dvwh t dw 20 25 25 ns t dveh t dw 20 25 25 ns output active from end of write (1) t whqx t wlz 000 ns 1. this parameter is guaranteed by design but not tested.
4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi81256c address data i/o read cycle 1 (we high; oe, cs low) t avqx t avqv t avav data 2 address 1 address 2 data 1 address data i/o data valid read cycle 2 (we high) t elqv t elqx t elicch t avav t ehqz t ehiccl icc cs high z ws32k32-xhx fig. 2 timing waveform - read cycle fig. 4 write cycle - cs controlled fig. 3 write cycle - we controlled address data in write cycle 2, cs controlled t aveh t eleh t ehax t wleh t dveh t ehdx t avav data valid high z we cs data out t avel address data in write cycle 1, we controlled t avwh t elwh t whax t wlwh t dvwh t wlqz t whqx t avwl t whdx t avav data valid high z we cs data out
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi81256c characteristic sym conditions min typ max units low power version only data retention voltage v dd v dd = 2.0v 2 C C v data retention quiescent current i ccdr cs 3 v dd -0.2v C 50 500 m a chip disable to data retention time (1) t cdr v in 3 v dd -0.2v 0 C C ns operation recovery time (1) t r or v in 0.2v t avav *C Cns note: 1. parameter guaranteed by design, but not tested. * read cycle time data retention characteristics (edi81256lp only) (t a = -55 c to +125 c) ws32k32-xhx fig. 5 data retention - cs controlled data retention, cs controlled data retention mode t r vcc cs t cdr cs = v dd -0.2v v dd 4.5v 4.5v
6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi81256c package 79: 28 pin ceramic flatpack all dimensions are in inches pin 1 0.019 0.015 0.045 0.026 0.180 min 0.130 0.100 0.050 bsc 0.420 0.380 1.00 typ 0.045 max 0.006 0.003 0.740 max 0.370 0.250 package 3: 24 pin sidebrazed ceramic dip (300 mils wide) pin 1 indicator 0.023 0.014 0.175 0.125 0.100 typ 11 x 0.100 = 1.100 0.200 max 1.280 max 0.098 max 0.320 0.290 0.060 0.015 package 14: 28 pad ceramic lcc all dimensions are in inches 0.050 0.560 0.360 0.340 0.540 0.120 0.060 0.050 typ 0.028 0.022 typ 0.095 0.075 all dimensions are in inches
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com edi81256c ordering information white electronic designs sram organization, 128kx8 technology: c = cmos standard power lp = low power access time (ns) package type: c = 32 lead sidebrazed dip, 300 mil (package 3) f = 32 lead ceramic flatpack (package 79) l = 32 pad ceramic lcc (package 14) device grade: b = mil-std-883 compliant m = military screened -55 c to +125 c i = industrial -40 c to +85 c c = commercial 0 c to +70 c edi 8 8 128 cs x x x
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